Semiconductor memory devices are integrated circuits in which information may be stored and from which information may be recalled when desired. Each memory device is built from a plurality of memory cells in which each memory cell has the capacity to store at least one binary bit of data. Essentially, the cells are located at intersections of wordlines and bitlines (e.g., visualized as rows and columns of an array). Cells may store a single bit of data as a logical “1” or a logical “0” and may sometimes be individually accessed or addressed. Cells may sometimes be addressed using two multi-bit numbers. When this scheme is used, the first multi-bit number, or row address, may identify the row of the memory array in which the memory cell is located. The second multi-bit number, or column address, may identify the column of the memory array in which the desired memory cell is located. Each row address/column address combination may correspond to a single memory cell.
Recalling data from memory arrays may not be perfectly accomplished in every case. Thus, error detection and correction schemes may be used to enhance memory array data storage reliability. However, most error correction schemes penalize overall operation of the array, perhaps in terms of circuit real estate and/or operational speed. Therefore, improved mechanisms for error detection/correction are needed.